As it is known by one skilled in the art, when a new computer system is designed it generally comprises defaults and/or bugs that need to be eliminated. In a computer system having a single master (such as a microprocessor, for instance) it is now an “easy” task to find the source or cause of a bug or error with a dedicated tool such as ETM (“Embedded Trace Module”) produced by ARM ltd. Indeed, the master and the slaves being connected to a main bus, it is possible to observe and control, through FIFO (“First In First Out”) memories, all kind of transfer on this main bus by connecting the dedicated tool to the system core pins.
In a computer system having several masters, such as a “multilayer ahb architecture” or a “parallelism architecture”, debugging and tracing are much more difficult because of the increasing number of masters and slaves to observe and control and/or the fact that several masters may work independently so that it becomes difficult to know what a master is doing towards the other masters. Moreover, in certain circumstances the internal speed of the system core may become so high that an overflow may occur in the FIFO memory assigned to one of the masters.
To solve this drawback it could be possible to assign a FIFO memory having a big size to each master, but this would required a very extensive area on the board, which is rarely available.